Embodiments relate to a semiconductor device and a method of fabricating the same, that may prevent diffusion of copper contained in a copper interconnection.
As information media, such as computers, have become more extensively used, there has been steady development in the semiconductor industry. Semiconductor devices may operate at a high speed, have large storage capacities, and have the ability to process large amounts of information. Semiconductor manufacturing technology has developed to improve the degree of integration, reliability, speed, and responsiveness of such devices.
Regarding highly integrated semiconductor devices, studies and research are being conducted in relation to copper (Cu), which has been identified as a next-generation metal interconnection material for a multi-layered metal interconnection. A metal interconnection using copper may be suitable for improving operational speed and resistance characteristics of a semiconductor device and may have superior parasitic capacitance between metal interconnections. Copper, however, exhibits poor etching properties. Accordingly, a damascene process may be used to fabricate a metal interconnection using copper.
According to the damascene process, a via hole and a trench extending from the via hole may be formed in a flat interlayer insulating layer. Metal may then be filled in the via hole and the trench.
Such copper metal interconnection may be formed in a semiconductor device having a multi-layered structure. The semiconductor device may be electrically connected to a package through a bonding process. To this end, a bonding pad may be provided on the copper metal interconnection of the semiconductor device.
As illustrated in example FIG. 1, interlayer dielectric layer 11 may be formed on a semiconductor substrate (not shown). Interlayer dielectric layer 11 may be formed at a predetermined area thereof with a via hole. In addition, barrier metal 13 maybe formed in the via hole. Copper metal interconnection 15 may be formed on barrier metal 13 provided in the via hole.
Copper metal interconnection 15 may protrude relative to interlayer dielectric layer 11, and may prevent a short circuit between copper metal interconnection 15 and interlayer dielectric layer 11 that may occur due to a copper metal interconnection adhering to interlayer dielectric layer 11. Thus, stepped area A may exist between a surface of copper metal interconnection 15 and a surface of interlayer dielectric layer 11.
Diffusion barrier 17 and aluminum metal layer 10 may be formed on copper metal interconnection 15.
Copper (Cu) contained in copper metal interconnection 15 may diffuse in the lateral direction (for example, as shown by the arrows). Although diffusion barrier 17 may be formed in stepped area A, a structure of diffusion barrier 17 formed at a side portion of copper metal interconnection 15 may be weak. Hence, copper diffusion may occur in the lateral direction.
Copper of copper metal interconnection 15 may diffuse into the whole area of aluminum metal layer 10 by passing through diffusion barrier 17 in the lateral direction. Due to such copper diffusion, copper may exist in a grain boundary in aluminum metal layer 10. Accordingly, the quality of a bonding pad obtained from aluminum metal layer 10 may be degraded and bonding defects may occur during the bonding process.